Field
The present disclosure relates to a display device and a manufacturing method thereof, and more particularly, to a thin film transistor substrate having a high aspect ratio and a manufacturing method thereof.
Description of Related Art
Liquid crystal displays (LCD) display an image by adjusting light transmittance of liquid crystal using an electric field. LCDs are classified as a vertical alignment (VA) LCD and an in-plane switching (IPS) LCD according to directions of an electric field driving liquid crystal.
In the VA LCD, a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate are disposed to face each other and twisted nematic (TN) mode liquid crystal is driven by a vertical field formed therebetween. The VA LCD advantageously has a large aperture ratio but disadvantageously has a narrow viewing angle of about 90 degrees.
In the IPS LCD, liquid crystal is driven in an IPS mode by an in-plane field between a pixel electrode and a common electrode disposed to be parallel each other on a lower substrate. The IPS LCD advantageously has a wide viewing angle, but disadvantageously has an aperture ratio smaller than that of the VA LCD.
FIG. 1 is a plan view illustrating a structure of a TFT substrate according to a related art. FIG. 2 is a cross-sectional view of the TFT substrate illustrated in FIG. 1, taken along line I-I′.
Referring to FIGS. 1 and 2, the related art TFT substrate includes a gate line GL and a data line DL intersecting with each other on a transparent lower substrate SUB. The gate line GL and the data line DL intersecting with each other with a gate insulating layer GI interposed therebetween define a pixel region in a matrix arrangement. On one side of the pixel region, there is disposed a TFT T including a gate electrode G branched from the gate line GL, a source electrode S branched from the data line DL, and a drain electrode D disposed to be spaced apart from the source electrode S by a predetermined interval and facing the source electrode D.
A semiconductor layer A overlapping the gate electrode G is formed on the gate insulating layer GI covering the gate electrode G. One side of the semiconductor layer A is in contact with the source electrode S, and the other side thereof is in contact with the drain electrode D.
A first insulating layer PAS for protecting an element and a second insulating layer PAC for planarization are sequentially formed on the TFT T. A pixel electrode PXL and a common electrode COM formed of a conductive material are formed on the second insulating layer PAC.
The pixel electrode PXL is in contact with the drain electrode D via a pixel contact hole PH penetrating through the second insulating layer PAC. Also, the pixel electrode PXL has a structure of the teeth of a comb in which a plurality of line segment shapes are arranged to be parallel at a predetermined interval within the pixel region.
The common electrode COM is connected to a common line CL disposed to be parallel to the gate line GL. The common line CL is formed on the same layer on which the gate line GL is formed and formed of the same material as that of the gate line GL. The common electrode COM is connected to the common line CL via a common contact hole CH penetrating through the first insulating layer PAS, the second insulating layer PAC, and the gate insulating layer GI.
An in-plane field horizontal in a direction of a surface of the lower substrate SUB is formed between the pixel electrode PXL and the common electrode COM to drive a liquid crystal layer disposed on the lower substrate SUB. A portion of the pixel electrode PXL is disposed to overlap the common line CL with the gate insulating layer GI, the first insulating layer PAS, and/or the second insulating layer PAC interposed therebetween. a Storage capacitor is formed in the overlap region.
In order to electrically connect lines and/or electrodes formed on mutually different layers and apply the same signal, a contact hole penetrating through the insulating layer interposed between the electrodes is formed. That is, as mentioned above, a pixel contact hole PH is formed to electrically connect the pixel electrode PXL and the drain electrode D, and a common contact hole CH is formed to electrically connect the common electrode COM and the common line CL.
Each of the contact holes PH and CH may need to be designed to have a sufficient area in order to reduce or prevent defective contact of the lines and/or the electrodes D, PXL, CL, and COM which are to be electrically connected. As the insulating layers PAS, PAC, and GI are thicker, the area of the contact holes PH and CH penetrating therethrough is increased. Also, when the plurality of contact holes PH and CH are disposed, a process margin may be required between the contact holes PH and CH.
In order to secure a region in which the contact holes PH and CH are disposed and a process margin region between the contact holes PH and CH, a sufficient space may need to be allocated. Such a space is a non-opening or a non-display area, and thus, may reduce aperture ratio. Also, in order to reduce or prevent generation of light leakage due to steps resulting from the contact holes PH and CH, a black matrix may be disposed in regions corresponding thereto. Here, since the black matrix is also a non-opening, the black matrix may also reduce aperture ratio.
These problems may become more severe in a high pixel-per-inch display device. That is, in a high resolution display device having a high PPI, a size of a single pixel is reduced, and thus, a size of contact holes PH and CH, and the like, may further reduce aperture ratio.